1. Field of the Invention
This invention relates to a semiconductor device that operates in synchronization with clock signal inputted from the outside, and particularly, to a semiconductor device which accepts write-data in synchronization with a data strobe signal.
2. Description of the Related Art
In general, microcomputers, Synchronous Dynamic Random Access Memory (hereafter referred to as SDRAM) or the like are known as semiconductor devices of integrated circuits or the like which operate in synchronization with a clock signal.
SDRAM are widely used as main memory of work stations or personal computers, and those with maximum operating frequency exceeding 100 MHz have been developed. With regard to workstations or the like, too, clock frequency of clock signal used is increasing year by year.
FIG. 25 shows an example of an information processing system including a plurality of SDRAM 102a, 102b, and 102c, and a CPU 103 for controlling these SDRAM 102a, 102b, and 102c that are installed on a printed wiring board 101. In the example, the CPU 103 outputs address signals AD, a control signal CTL, and a clock signal CLK to each of the SDRAM 102a, 102b, and 102c. The CPU 103 and each of the SDRAM 102a, 102b, and 102c input and output data signals DQ which is an input/output signal.
FIG. 26 shows the operation timing when the CPU 103 reads out data stored in the SDRAM 102a, 102b, and 102c. Here, although FIG. 26 also puts in rows, the operation timing of SDRAM 102a, 102b, and 102c, the CPU 103 actually accesses each SDRAM 102a, 102b, and 102c at different timings, respectively.
Now, propagation delay time of the signal transmitted between the CPU 103 and each of the SDRAM 102a, 102b, and 102c differs according to the wiring pattern length on the printed wiring board 101 of each signal. In this example, the propagation delay time is shortest between the SDRAM 102a and the CPU 103, and longest between the SDRAM 102c and the CPU 103. Therefore the clock signal CLK, the control signal CTL, and the address signals AD that are outputted from the CPU 103 are transmitted in the order of SDRAM 102a, 102b, and 102c. The SDRAM 102a, 102b, and 102c accept the control signal CTL and the address signals AD in synchronization with the clock signal CLK inputted into respective SDRAM at different timings, read out read-data from memory cells selected by the address signals AD when the control signal CTL instructs reading out, and output, as a data signals DQ, the read-data which is read out. In this process, the read-data from the SDRAM 102a is outputted earliest and the read-data from the SDRAM 102c is outputted latest. That is, skew (deviation of output timing) according to propagation delay time due to the wiring pattern length occurs when outputting the read-data.
The CPU 103 accepts, at a predetermined timing, the data signals DQ outputted from the SDRAM 102a, 102b, and 102c. The timing of accepting the data signals DQ by the CPU 103 is set in accordance with the SDRAM 102c, which outputs the data signals DQ latest, in order to accept the data signals DQ with reliability.
On the other hand, when writing data into the SDRAM 102a, 102b, and 102c, deviation between the timings of receiving the data signals DQ and the address signals AD occurs at the SDRAM 102a, 102b, and 102c, even if the address signals AD and the data signals DQ are outputted from the CPU 103 in synchronization with each other. This is because, although the wiring pattern lengths of the address signals AD and the data signals DQ connecting the CPU 103 and each of the SDRAM 102a, 102b, and 102c are roughly the same, their wiring capacities differ.
Here, while an example is shown in FIG. 25 wherein the clock signal CLK is generated inside the CPU 103, the clock signal CLK, when generated in a device other than the CPU 103, causes a large skew as shown in FIG. 26 in the write operation as in the case with the read operation.
The skew generated by the propagation delay time depending on the above-mentioned wiring pattern length is determined by wiring resistance and wiring capacitance but will not be affected by change of clock frequency. Therefore the skew becomes relatively larger as the clock frequency is set higher. This results in a problem that, in the case of read operation, timing design of an information processing system becomes difficult when the skew of the data signals DQ accepted by the CPU 103 becomes equal to or higher than a predetermined ratio relative to the cycle of the clock signal CLK.
In order to solve the problem, a new type of SDRAM has been proposed, which includes a synchronization signal DS (data strobe signal) specific for write/read of the data signals DQ.
The data strobe signal DS is outputted from the CPU in synchronization with the data signals DQ when the data is transmitted from the CPU to the SDRAM, whereas it is outputted from the SDRAM in synchronization with the data signals DQ when the data is transmitted from the SDRAM to the CPU. Besides, since the wiring pattern of the data strobe signal DS formed on the printed wiring board has nearly the same wiring length/wiring capacitance as those with the wiring pattern of corresponding data signals DQ, the device at the receiving side of the data signals DQ can receive the data signals DQ at a correct timing in synchronization with the data strobe signal DS.
FIGS. 27 to 30 show an exemplary composition proposed by the present inventors in order to implement an SDRAM having an input/output functionality of the data strobe signal DS. Here the SDRAM shown in FIGS. 27 to 30 is not yet known.
In FIG. 27, the SDRAM 105 comprises an input/output interface unit 106, a memory control interface unit 107, and a memory cell array 108.
The clock signal CLK, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE, the address signals AD, the data signals DQ, and a data strobe signal DS are supplied to the input/output interface unit 106. The address signals AD and the data signals DQ or the like, which are denoted by thick arrows in the figure, are signals consisting of a plurality of bits.
The "/" expression such as /CS, /RAS or the like, implies negative logic, i.e., the signal is activated when it is at LOW level. The data signals DQ and the data strobe signal DS are input/output signals. In this example, SSTL-2 (Stub Series Terminated Transceiver Logic-2) interface is applied as an interface specification, wherein an information processing system including the SDRAM 105 is required to have the signal line for transmitting the data signals DQ and the data strobe signal DS terminated at a predetermined voltage.
The input/output interface unit 106 has a clock buffer 109, a command decoder 110, an address buffer 111, an input/output data buffer 112, and a DS input/output control circuit 113.
The clock buffer 109 receives an external clock signal CLK and outputs an internal clock signal CLKIN, denoted by the dashed line in the figure, to the outside.
The command decoder 110 receives the chip select signal /CS, the row address strobe signal /RAS, the column address strobe signal /CAS, and the write enable signal /WE, and outputs a command signal CMD according to the signal levels of these control signals /CS, /RAS, /CAS, and /WE to the memory control interface unit 107 and the DS input/output control circuit 113. The command decoder 110 determines that a "write command" is inputted and sets the write activate signal WRTZ that is one of command signals CMD to HIGH level when the control signals are, for example, such as /CS=LOW level, /RAS=HIGH level, /CAS=LOW level, and /WE=LOW level.
The address buffer 111 receives the address signals AD, converts the received address signals AD into internal address signals ADIN, and outputs the ADIN to the memory control interface unit 107.
The input/output data buffer 112 performs input/output operation of the data signals DQ with the outside, while performing input/output operation of I/O signals DIN with the memory cell array 108.
The DS input/output control circuit 113 performs input/output operation of the data strobe signal DS with the outside, and receives the write activate signal WRTZ. The DS input/output control circuit 113 controls the input/output timing of the data signals DQ in the input/output data buffer 113.
The memory control interface unit 107 has a control circuit 114 for performing timing control of the entire SDRAM 105, a mode register 115 for setting the operation modes such as the Burst Length which is the number of transfers when successively transferring the data signals DQ or latency, and a burst counter 116 for counting the above-mentioned burst length.
A plurality of memory cells, not shown, are arranged in rows and columns in the memory cell array 108. Control signals RAS, CAS, and WE generated from the control signals /RAS, /CAS, and /WE, and row address signals, column address signals, and the I/O signals DIN are connected between the memory cell array 108 and the memory control interface unit 107.
Here, as SDRAM 105 of this kind, Single Data Rate type (hereinafter SDR type) which performs write/read of the data signals DQ in synchronization with only the leading edge of the data strobe signal DS, and Double Data Rate type (hereinafter DDR type) which performs write/read operations of the data signals DQ in synchronization with both the leading edge and the trailing edge of the data strobe signal DS have been proposed.
FIG. 28 shows an exemplary information processing system including an SDRAM 105 having a data strobe signal DS and a memory control circuit 118 for controlling the SDRAM 105 on a printed wiring board 117. The memory control circuit 118 comprises, for example, a CPU 119 and a clock control circuit 120.
Each of the control signals /CS, /RAS, /CAS, and /WE of the memory control circuit 118 and the SDRAM 105, and the address signals AD, the data signals DQ, the clock signal CLK, and the data strobe signal DS are connected to each other by the trace wiring formed on the printed wiring board 117. Additionally, the signal line which is an input/output terminal for transmitting the data signals DQ and the data strobe signal DS is connected, via a terminating resistor 121, to a predetermined voltage VTT defined by the SSTL-2 interface. Therefore, when both the memory control circuit 118 and the SDRAM 105 are driving neither the data signals DQ nor the data strobe signal DS, the voltage level of the data signals DQ or the data strobe signal DS has become the terminal voltage VTT. Here, the voltage VTT is set to half the value of the supply voltage for the input/output signal line.
FIG. 29 shows an example of operation timing when the memory control circuit 118 writes data into the DDR type SDRAM 105, in the information processing system shown in FIG. 28. In this example, the "burst length" is set to "4". At the time of write operation, the clock signal CLK, the data strobe signal DS, and the data signals DQ are outputted by the memory control circuit 118. The write activate signal WRTZ and the I/O signals DIN are signals used in the internal circuit of the SDRAM 105 shown in FIG. 27. The timings of the address signals AD and the control signals /CS, /RAS, /CAS, and /WE are omitted.
First, the memory control circuit 118 inputs write command into the SDRAM 105 by setting the control signals /CS, /RAS, /CAS, and /WE to a predetermined value in synchronization with the leading edge of the clock signal CLK.
The SDRAM 105, upon input of the write command, sets the write activate signal WRTZ to HIGH level, and activates the input/output data buffer 112 via the DS input/output control circuit 113 shown in FIG. 27. The activating turns the input/output buffer 112 into a state capable of accepting the data signals DQ.
Next, the memory control circuit 118 sets the data strobe signal DS to LOW level within a predetermined time period (about a half clock delay in the example of FIG. 29) from the rising of the clock signal CLK when the write command is received. Then, rise and fall of the data strobe signal DS is repeated the number of times equal the "burst length" with the same periodicity as that of the clock signal CLK, and simultaneously, write-data D0, D1, D2, D3 are inputted to the data terminal DQ.
Here, although the timing of the first rise of the data strobe signal DS (time 1 of FIG. 29) is defined to be one clock period later than the timing of the rise of the clock signal CLK in synchronization with the receipt of the write command, a phase deviation of .+-.25% relative to the rise of the clock signal CLK at time 1 is allowed.
The SDRAM 105 accepts write-data D0, D1, D2, D3 sequentially in synchronization with the leading edge and the trailing edge of the data strobe signal DS. The SDRAM 105 outputs the accepted write-data D0, D1, D2, D3 to the memory cell array 108 via the internal I/O signals DIN.
The SDRAM 105 counts up the burst counter 116 shown in FIG. 27 each time the clock signal CLK rises after receipt of the write command. In the case with the DDR type, counting by the burst counter 116 is performed the number of times which is half as much as the "burst length".
In the example shown in FIG. 29, having allowed a predetermined time period after the burst counter 116 counted "2", which is half the "burst length (4)", the command decoder 110 sets the write activate signal WRTZ to LOW level, and inactivates the input/output data buffer 112.
The above-mentioned predetermined time period from the end of counting to the setting of the write activate signal WRTZ to LOW level is generated by a delay circuit such as a time constant circuit, being composed of capacitors and resistors. Also, the predetermined time period is set so that the final write-data D3 can be accepted with reliability, even if the ambient temperature and the supply voltage varied within specification, and the phase of the data strobe signal DS delayed relative to the clock signal by +25%.
That is, when the burst length is constant, the timing at which the write activate signal WRTZ turns from HIGH level to LOW level (inactivated) does not change regardless of the phase deviation (within .+-.25%) of the data strobe signal DS relative to the clock signal CLK, and remains the same as the inactivate timing of the write activate signal WRTZ when the above-mentioned deviation is +25% (the phase of the data strobe signal DS delayed relative to the clock signal CLK by 25%).
The memory control circuit 118 maintains the data strobe signal DS at LOW level for a period as long as about half clock after the trailing edge, being in synchronization with the final write-data D3, of the data strobe signal DS. Then, the memory control circuit 118 stops outputting the data strobe signal DS. Therefore, the voltage level of the data strobe signal DS becomes the terminal voltage VTT supplied via the terminating resistor 121. And the write operation is completed.
Now, as described above, the phase of the data strobe signal DS outputted from the memory control circuit 118 is allowed to deviate within a predetermined range (.+-.25% in the above-mentioned example) relative to the clock signal CLK. Also the inactivate timing of the write activate signal WRTZ is set to be in accordance with the case in which the phase of the data strobe signal DS delays by 25% relative to the clock signal (+25%).
Therefore, as shown in FIG. 30, in a timing design wherein the phase of the data strobe signal DS outputted from the memory control circuit 118 is designed to deviate by -25% (earlier by 25%) relative to the clock signal CLK, there is a possibility that a period HZ may arise during which the write activate signal WRTZ remains at HIGH level after the receipt operation of the write-data has completed and the data strobe signal DS has become the terminal voltage VTT.
There has been a problem that, during the period HZ, noise may be generated in the data strobe signal DS due to influence of noise from the power source or the like, and, if the noise is transmitted into the SDRAM 105, erroneous data may be accepted after the final write-data D3, as shown in FIG. 30. This may result in writing erroneous data into the memory cell array 108 and destroying the valid data.